In this paper, we propose a model for the LDMOS transistor used for power
amplification in the frequencies band 1.8–2.2 GHz dedicated to the mobile
telephony system Digital Cellular System (DCS). This model takes into account the
behaviour of each internal region of the power structure. A new representation of the
non-linear inter-electrode capacitances, drain-gate Cgd and drain-source Cds, is
proposed. The obtained model is implemented in the circuit simulator PSPICE, which
gives an overall evaluation of the transistor performances in the radio frequency
power amplification mode. This model is Maynly intended to the system designer. A
study of the power amplification in the SHF band at 2 GHz is performed. A good
agreement between experimental and simulation results is found.